A memory device, particularly an SDRAM which has large capacity among semiconductor memory devices, is widely used as a frame memory in an image processing device. For a frame memory which stores image data, a larger capacity is strongly demanded to support a full high vision screen. On the other hand, high-speed accessing to image data in an arbitrary area, in addition to normal memory access based on raster scan, is demanded to support the MPEG standard, having compression and decompression processing of moving pictures. For example, the MPEG standard includes processing to search an image that matches an image in a predetermined rectangular area in order to detect a motion vector. For this motion vector search processing, a frequent and large capacity read operation to a frame memory is required.
The present applicant applied for patents for a memory device which has access function to support various image processings. Japanese Patent Application No. 2006-345415 (filed on Dec. 22, 2006, Japanese laid-open Patent 2008-159131), is an example. According to this application, a memory device has a plurality of memory unit areas which are selected by an input address, image data is stored in the plurality of memory unit areas according to a predetermined memory map, and output data is read from adjacent memory unit areas, and input data is written to the adjacent memory unit areas by providing the input address once.
An SDRAM has burst read and burst write functions, and can efficiently access the storage areas within continuous addresses. Therefore in the case of a memory map for storing two-dimensional image data in the raster scan direction in continuous address areas, access for raster scanning the two-dimensional image data becomes very efficient, and the bandwidth of the memory, which indicates a number of data that can be processed in a unit time, becomes very wide. However accessing memory in a direction or in an area that is different from the raster scan drops memory access efficiency, and decreases the bandwidth of the memory.
In order to solve this problem of an SDRAM, various proposals have been made. Patent Documents 1 to 5 are examples thereof.
Patent Document 1 discloses that a plurality of rows of image data are simultaneously accessed by storing image data on a two-dimensional image in a vertical direction in an area having a same row address and column address in a plurality of bank areas in a memory, and activating the plurality of bank areas simultaneously. In other words, efficiency to access a plurality of rows of image data is increased by storing image data on a two-dimensional image based on a special memory map.
Patent Document 2 discloses that a video RAM (VRAM) has a DRAM for storing image data on a two-dimensional image, and a serial access memory SAM which cache-controls the data in the DRAM, the serial access memory SAM has a serial address counter which can count addresses in ascending order or descending order, and a horizontally reversed image is written in the DRAM by the serial address counter counting in descending order.
Patent Document 3 discloses that a video RAM (VRAM) has a DRAM for storing image data on a two-dimensional image and a serial access memory SAM which cache-controls the data in the DRAM, an address counter of the serial access memory can be changed to addition mode or subtraction mode, and an addition value of the address counter can be set from the outside as an arbitrary number.
Patent Document 4 discloses that image data read by an image reading device is written to an image memory, so that the addresses of image data, which are next to each other in the secondary scanning direction, are to be continuous addresses, and for the image data which is read in a vertically and horizontally reversed manner, page mode read processing is performed.
Patent Document 5 discloses a video RAM similar to Patent Document 2.    Patent Document 1: Japanese Patent Application Laid-Open No. 2005-116128    Patent Document 2: Japanese Patent Application Laid-Open No. H8-190372    Patent Document 3: Japanese Patent Application Laid-Open No. H6-243675    Patent Document 4: Japanese Patent Application Laid-Open No. H5-334426    Patent Document 5: Japanese Patent Application Laid-Open No. H5-54657